1. Field of the Invention
The present invention relates to a differential amplifier circuit, which is capable of performing a low voltage operation and obtaining amplification having a high gain even under the power supply from a power source of a low voltage.
2. Description of the Related Art
As a differential amplification circuit, which performs a high gain differential amplification, there has been conventionally used a differential amplifier circuit as shown in FIG. 1.
More specifically, PNP transistors Q3 and Q4 are disposed between collectors of an input differential pair of NPN transistors Q1 and Q2 and a power source Vcc. Each collector of PNP transistors Q3 and Q4 is connected to each of the corresponding NPN transistors Q1 and Q2. The emitters of PNP transistors Q3 and Q4 are connected to the power source vcc. A load resistor R1 is connected between a contact point, which is between the collector of the NPN transistor Q1 and that of the PNP transistor Q3, and the bases of the PNP transistors Q3 and Q4. A load resistor R2 is connected between a contact point, which is between the collector of the NPN transistor Q2 and that of the PNP transistor Q4, and the bases of the PNP transistors Q3 and Q4.
The bases of the transistors Q1 and Q2 are connected to a reference power voltage Vref in common. The emitters of the transistors Q1 and Q2 are connected to a bias current source IBias.
In the conventional differential amplifier circuit of FIG. 1, since a current, which flows to the load resistor in a non-signal state, is used as a base current for the PNP transistors Q3 and Q4, voltage drop can be controlled to be small even if a relatively large resistor is used as a load resistor to obtain the amplifier having a high gain. Therefore, the differential amplifier circuit shown in FIG. 1 has been conventionally used as a high gain amplifier for a low voltage operation.
The following will explain a case in which the conventional differential amplifier circuit is used with a power voltage of about Vcc=0.9 V.
The voltage of each collector of the NPN transistors Q1 and Q2 is set to the value at which the base-emitter voltage VBE of the PNP transistors Q3 and Q4 forming an active load is dropped by 0.7 V from the power voltage vcc. Due to this, in order to set each collector-emitter voltage of the differential pair within a saturation voltage (vsat=0.15) of the transistor in a state that the power voltage vcc is 0.9 V, the voltage between the common emitter of the NPN transistors Q1 and Q2 and a pair ground voltage (common lowest voltage) must be set to 50 mv. Therefore, since the transistor having the saturation voltage Vsat cannot be used, the use of the transistor is limited to a current bias system using a resistor. This causes the bias current change of the differential pair due to the input bias voltage and the reduction of the voltage conversion gain to the input signal voltage. As a result, the characteristic of the differential amplifier circuit is deteriorated.
In the differential amplifier circuit of FIG. 1, the voltage VBE of the PNP transistors forming an active load is the voltage, which is dropped from the power voltage, so that there is no room for performing a reducing voltage operation by the output of each collector of the NPN transistors.